Integrated circuit memory devices are widely used in consumer and commercial applications to store data. As is well known to those having skill in the art, integrated circuit memory devices generally include an array of memory cells. In order to increase manufacturing efficiencies, integrated circuit memory devices typically include an array of memory cells which has a selectable path width. As is well known to those having skill in the art, the path width, which reflects the number of data input/output channels, also referred to as "DQ" channels, can vary for a given size of memory. Thus, for example, a 16 megabit dynamic RAM (DRAM) array may be configured during manufacture to operate with a 4 bit data path width, so that a 4 megabit.times.4 DRAM is provided. Alternatively, the 16 megabit DRAM may be configured to operate as a 1 megabit.times.16 DRAM, so that a 16 bit wide data path is provided.
In one illustrative example, Samsung Electronics Co., Ltd., the assignee of the present invention, markets a family of 16 megabit CMOS DRAMs, as 4 megabit.times.4 bit DRAMs and 1 megabit.times.16 bit DRAMs. In particular, Model Nos. KM44C4004A, KM44C04104A, KM44V004A and KM44V4104A are marketed as 4 megabit.times.4 bit DRAMs. See Samsung Electronics 1995 Databook, Pages 46-47. Models KM416C1004A, KM416C1204A, KM416V1004A and KM416V1204A are marketed as 1 megabit.times.16 bit CMOS DRAMs. See Pages 62-63 of the aforesaid 1995 Databook. An integrated circuit memory in which 16 bits of data is simultaneously read from and written to a memory device via 16 DQ channels is referred to as operating in "x16" mode. Similarly, an integrated circuit memory device in which 4 data bits are simultaneously read from and written to a memory device via 4 DQ channels is referred to as operating in "x4" mode.
Integrated circuit memory devices may be designed and manufactured to include both the x16 and the x4 mode in a single integrated circuit. During manufacturing, either x16 mode or x4 mode is selected to produce, for example, a 4 megabit by 4 bit DRAM or a 1 megabit.times.16 bit DRAM. Selection of the mode is generally performed by generating permanent selection signals during manufacturing. In particular, an x16 bonding pad and an x4 bonding pad are provided in the integrated circuit. One of the bonding pads is tied to ground or power supply voltage to permanently produce either an x16 or an x4 signal. FIGS. 1A and 1B are circuit diagrams of a conventional x16 mode selection signal generator and an x4 mode selection signal generator, respectively.
Referring now to FIG. 1A, the x16 mode selection signal generator includes an x16 bonding pad which receives a bonding signal, such as a permanently bonded power supply voltage, ground or other permanent signal. A transfer transistor MN1 transfers the bonding signal. Inverters I1, I2 and I3 serially invert the transferred bonding signal. A pull-up transistor MP1 is always turned on and is connected to the output terminal of the transfer transistor MN1.
Similarly, in FIG. 1B, the x4 mode selection signal generator includes an x4 bonding pad which receives a bonding signal and a transfer transistor MN2 which transfers the bonding signal. Inverters I4, I5 and I6 serially invert the transferred bonding signal, and a pull-up transistor MP2 is connected to the output terminal of the transfer transistor MN2.
Accordingly, if the x16 bonding pad of FIG. 1A is permanently connected to ground voltage VSS, the output signal x16 is always set to the power supply voltage VDD. The signal x16 is then applied to the array of memory cells so that the integrated circuit memory device always operates in x16 mode. Alternatively, if the x4 bonding pad of FIG. 1B is bonded to VSS, the output signal x4 of FIG. 1B is maintained at high level VDD and the integrated circuit memory device will operate in x4 mode.
As stated above, during manufacture, the integrated circuit memory device is set for either x16 mode or x4 mode and is identified, marketed and operated accordingly.